Optimized Testing Of Quantum-logic Circuits
A method and associated systems for using direct sums and invariance groups to optimize the testing of partially symmetric quantum-logic circuits is disclosed. A test system receives information that describes the architecture of a quantum-logic circuit to be tested. The system uses this information to organize the circuit's inputs into two or more mutually exclusive subsets of inputs. The system computes a direct sum of a set of groups associated with the subsets in order to generate an invariance group that contains one or more invariant permutations of the circuit's inputs. These invariant permutations can be used to reduce the number of tests required to fully verify the circuit for all possible input vectors. Once one specific input vector has been verified, there is no need to test other vectors that can be generated by performing any one of the invariant permutations upon the previously verified vector.
Much More than Average Length Specification
- Claim CLM-00001. 1. A quantum-logic test-development system comprising a processor, a memory coupled to the processor, and a computer-readable hardware storage device coupled to the processor, the storage device containing program code configured to be run by the processor via the memory to implement a method for reducing complexity when testing quantum-logic circuits, the method comprising:
the system optimizing a procedure for testing a quantum-logic circuit that has at least four inputs and at least one output,
where the procedure comprises a series of tests that each verify that the quantum-logic circuit is placed in a particular output state in response to receiving a distinct input vector of a set of input vectors; and
the system deleting from the series of tests a test that, when completed successfully by the quantum-logic circuit, does not change an existing output state of the quantum-logic circuit that had resulted from a successful performance of another test of the series of tests.
- Claim CLM-00008. 8. A method for reducing complexity when testing quantum-logic circuits, the method comprising:
a quantum-logic test-development system optimizing a procedure for testing a quantum-logic circuit that has at least four inputs and at least one output,
where the procedure comprises a series of tests that each verify that the quantum-logic circuit is placed in a particular output state in response to receiving a distinct input vector of a set of input vectors; and
the system deleting from the series of tests a test that, when completed successfully by the quantum-logic circuit, does not change an existing output state of the quantum-logic circuit that had resulted from a successful performance of another test of the series of tests.
- Claim CLM-00016. 16. A computer program product, comprising a computer-readable hardware storage device having a computer-readable program code stored therein, the program code configured to be executed by a quantum-logic test-development system comprising a processor, a memory coupled to the processor, and a computer-readable hardware storage device coupled to the processor, the storage device containing program code configured to be run by the processor via the memory to implement a method for reducing complexity when testing quantum-logic circuits, the method comprising:
optimizing a procedure for testing a quantum-logic circuit that has at least four inputs and at least one output,
where the procedure comprises a series of tests that each verify that the quantum-logic circuit is placed in a particular output state in response to receiving a distinct input vector of a set of input vectors; and
deleting from the series of tests a test that, when completed successfully by the quantum-logic circuit, does not change an existing output state of the quantum-logic circuit that had resulted from a successful performance of another test of the series of tests.
