Magic State Distillation With Low Space Overhead And Asymptotic Input Count
Disclosed herein are example embodiments of protocols to distill magic states for T-gates. Particular examples have low space overhead and use an asymptotically optimal number of input magic states to achieve a given target error. The space overhead, defined as the ratio between the physical qubits to the number of output magic states, is asymptotically constant, while both the number of input magic states used per output state and the T-gate depth of the circuit scale linearly in the logarithm of the target error. Unlike other distillation protocols, examples of the disclosed protocol achieve this performance without concatenation and the input magic states are injected at various steps in the circuit rather than all at the start of the circuit. Embodiments of the protocol can be modified to distill magic states for other gates at the third level of the Clifford hierarchy, with the same asymptotic performance. Embodiments of the protocol rely on the construction of weakly self-dual Calderbank-Shor-Steane codes (“CSS codes”) with many logical qubits and large distance, allowing one to implement control-Swaps on multiple qubits. This code is referred to herein as the “inner code”. The control-Swaps are then used to measure properties of the magic state and detect errors, using another code that is referred to as the “outer code”. Alternatively, one can use weakly-self dual CSS codes which implement controlled Hadamards for the inner code, reducing circuit depth. Several specific small examples of this protocol are disclosed herein.
Claim CLM-00001. 1. A method for distilling magic states in a topological quantum computing device, comprising:
in the topological quantum computing device:
applying an inner code comprising a weakly self-dual error correcting code to implement control-Swap operations on a plurality of qubits or qudits; andusing the control-Swap operations to test properties of the magic states on the plurality of qubits or qudit so that a distance of the code scales proportional to the number of logical qubits or qudits,wherein the topological quantum computing device uses Majorana zero modes to implement the plurality of qubits or qudits.
Claim CLM-00009. 9. A circuit configured to distill magic states in a quantum computing device, comprising:
quantum circuit elements configured to implement an inner code and an outer code, the inner code providing a weakly self-dual error correcting code to implement control-Swap operations on a plurality of logical qubits or qudits and provide error suppression to a target power, the outer code providing an error-correcting code with a sensitivity selected to test the properties of the magic states such that measurement errors are also suppressed by the target power, wherein the circuit is part of a topologically protected quantum computer using Majorana zero modes to implement qubits or qudits.
Claim CLM-00018. 18. A method for distilling magic states in a topologically protected quantum computing device that uses Majorana zero modes to implement physical qubits or qudits, comprising:
in the topologically protected quantum computing device that uses Majorana zero modes to implement the physical qubits or the qudits:
applying an inner code and couter code to distill a plurality of the magic states in the quantum computing device, and thereby possible error in the magic states,wherein the inner code comprises Bose-Chaudhuri-Hocquenghem (“BCH”) codes to implement operations on a plurality of the physical qubits or qudits in the quantum computing device, andwherein error correction is implemented on the inner code.
Claim CLM-00020. 20. A circuit configured to distill magic states in a quantum computing device, comprising:
quantum circuit elements configured to implement an inner code and an outer code, wherein the inner code provides a weakly self-dual error correcting code to implement control-Swap operations on a plurality of logical qubits or qudits, wherein the outer code provides an error-correcting code, wherein the inner code and the outer code are concatenated with one or more stabilizer codes, and wherein the circuit is part of a topologically protected quantum computer using Majorana zero modes to implement the plurality of logical qubits or qudits.
