Application US20190146541

ALTERNATINGLY-SWITCHED PARALLEL CIRCUIT, INTEGRATED POWER MODULE AND INTEGRATED POWER PACKAGE
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US20190146541

1. An alternatingly-switched parallel circuit comprising a first bridge arm and a second bridge arm, wherein (7) (2)

the first bridge arm comprises: a first upper bridge-arm switch comprising a first terminal, a second terminal and a control terminal; and

a first lower bridge-arm switch comprising a first terminal, a second terminal and a control terminal;

wherein the second terminal of the first upper bridge-arm switch is electrically connected to the first terminal of the first lower bridge-arm switch:

the second bridge arm comprises: a second upper bridge-arm switch comprising a first terminal, a second terminal and a control terminal; and

a second lower bridge-arm switch comprising a first terminal, a second terminal and a control terminal;

wherein the second terminal of the second upper bridge-and switch is electrically connected to the first terminal of the second lower bridge-arm switch;

wherein the first bridge arm and the second bridge arm are at least partly formed in a chip including a plurality of first cell groups and a plurality of second cell groups;

wherein the plurality of first cell groups are configured to form one of the first upper bridge-arm switch of the first bridge arm and the first lower bridge-arm switch of the first bridge arm, and the plurality of second cell groups are configured to form one of the second upper bridge-arm switch of the second bridge arm and the second lower bridge-arm switch of the second bridge arm; and

the plurality of first cell groups and the plurality of second cell groups are switched on and off alterantingly;

wherein the plurality of first cell groups are disposed in a first region of the chip, and the plurality of second cell groups are disposed in a second region of the chip;

wherein the first region contains a plurality of first sub-regions, and the second region contains a plurality of second sub-regions, and the first sub-regions and the second sub-regions are arranged alternatingly.

2. The alternatingly-switched parallel circuit according to claim 1, wherein the plurality of first cell groups are configured to form the first upper bridge-arm switch of the first bridge arm and the plurality of second cell groups are configured to form the second upper bridge-arm switch of the second bridge arm. (0)

3. The alternatingly-switched parallel circuit according to claim 1, wherein the plurality of first cell groups are configured to form the first lower bridge-arm switch of the first bridge arm and the plurality of second cell groups are configured to form the second lower bridge-arm switch of the second bridge arm (0)

4. The alternatingly-switched parallel circuit according to claim 1, further comprising: (0) (3)

a first inductor comprising a first terminal and a second terminal the first terminal of the first inductor being electrically connected to the second terminal of the first upper bridge-arm switch and the first terminal of the first lower bridge-arm switch; and

a second inductor comprising a first terminal and a second terminal, the first terminal of the second inductor being electrically connected to the second terminal of the second upper bridge-arm switch and the first terminal of the second lower bridge-arm switch;

wherein the second terminal of the first inductor is electrically connected to the second terminal of the second inductor

5. The alternatingly-switched parallel circuit according to claim 1, wherein the plurality of first cell groups and the plurality of second cell groups are switched on and off in the interleaved mode with a phase difference of 180 degrees, 120 degrees or 90 degrees. (0)

6. The alternatingly-switched parallel circuit according to claim 1, wherein the plurality of first cell groups have a plurality of first external pins, the plurality of second cell groups have a plurality of second external pins, a geometric center of at least one of the first external pins and the second external pins overlaps with a surface of the chip. (0)

7. The alternatingly-switched parallel circuit according to claim 1, wherein each of the first sub-regions and the second sub-regions is in a stripe shape, or each of the first sub-regions and the second sub-regions is in a polygon shape. (0)

8. The alternatingly-switched parallel circuit according to claim 1, wherein the alternatingly-switched parallel circuit is a BUCK circuit, a BOOST circuit, a Totem-Pole circuit, a BUCK-BOOST circuit or a full-bridge circuit. (0)

9. An integrated power module, which is applied in an alternatingly-switched parallel circuit comprising a first bridge arm and a second bridge arm, wherein (3) (3)

the first bridge arm comprises: a first upper bridge-arm switch comprising a first terminal, a second terminal and a control terminal; and

a first lower bridge-arm switch comprising a first terminal, a second terminal and a control terminal;

a first electrode electrically connected to the first terminal of the first upper bridge-arm switch;

a second electrode electrically connected to the second terminal of the first lower bridge-arm switch; and

a third electrode electrically connected to the second terminal of the first upper bridge-arm switch and the first terminal of the first lower bridge-arm switch;

the second bridge arm comprises: a second upper bridge-arm switch comprising a first terminal, a second terminal and a control terminal, the first electrode being electrically connected to the first terminal of the second upper bridge-arm switch;

a second lower bridge-arm switch comprising a first terminal, a second terminal and a control terminal, the second electrode being electrically connected to the second terminal of the second lower bridge-arm switch; and

a fourth electrode electrically connected to the second terminal of the second upper bridge-arm switch and the first terminal of the second lower bridge-arm switch;

the integrated power module further comprises: a first inductor comprising a first terminal and a second terminal, the first terminal of the first inductor being electrically connected to the third electrode; and

a second inductor comprising a first terminal and a second terminal, the first terminal of the second inductor being electrically connected to the fourth electrode;

wherein one of the first upper bridge-arm switch of the first bridge arm and the first lower bridge-arm switch of the first bridge arm and one of the second upper bridge-arm switch of the second bridge arm and the second lower bridge-arm switch of the second bridge and are formed in a chip, and the chip includes a plurality of first cell groups and a plurality of second cell groups;

wherein the plurality of first cell groups and the plurality of second cell groups are switched on and off alternatingly;

wherein the plurality of first cell groups are disposed in a first region of the chip, and the plurality of second cell groups are disposed in a second region of the chip;

10. The integrated power module according to claim 9, wherein the first upper bridge-arm switch of the first bridge arm and the second upper bridge-arm switch of the second bridge arm are formed in the chip; (0) (1)

11. The integrated power module according to claim 9, wherein the first lower bridge-arm switch of the first bridge arm and the second lower bridge-arm switch of the second bridge arm are formed in the chip; (0) (1)

12. The integrated power module according to claim 9, wherein each of the first sub-regions and the second sub-regions is in a stripe shape, or each of the first sub-regions and the second sub-regions is in a polygon shape. (0)

13. An integrated power package, which is applied in a power circuit composing a first bridge arm and a second bridge arm, the first bridge arm comprising a first upper bridge-arm switch and a first lower bridge-arm switch, the second bridge arm comprising a second upper bridge-arm switch and a second lower bridge-arm switch, (5) (5)

wherein the integrated power package comprises a first switch and a second switch, the first switch and second switch are formed in a chip, and the chip includes a plurality of first cell groups and a plurality of second cell groups;

wherein the plurality of first cell groups are configured to form the first switch as one of the first upper bridge-arm switch of the first bridge arm and the first lower bridge-arm switch of the first bridge arm, and the plurality of second cell groups are configured, to form the second switch as one of the second upper bridge-arm switch of the second bridge arm and the second lower bridge-arm switch of the second bridge arm, and

the plurality of first cell groups and the plurality of second cell groups are switched on and off alternatingly;

wherein the plurality of first cell groups are disposed in a first region of the chip, and the plurality of second cell groups are disposed in a second region of the chip;

14. The integrated power package according to claim 13, each of the first sub-regions and the second sub-regions is in a stripe shape, or each of the first sub-regions and the second sub-regions is in a polygon shape. (0)

15. The integrated power package according to claim 13, wherein the power circuit further comprises a capacitor connected in parallel with the first bridge arm and the second bridge arm; wherein the capacitor is formed in the chip or package. (0)

16. The integrated power package according to claim 13, wherein the plurality of first cell groups are configured to form the first upper bridge-arm switch of the first bridge arm, and the plurality of second cell groups are configured to form the second upper bridge-arm switch of the second bridge arm. (1) (0)

17. The integrated power package according to claim 16, further comprising a third switch and a fourth switch, wherein the third switch and the fourth switch are formed in the chip, (1) (2)

19. The integrated power package according to claim 13, wherein the plurality of first cell groups are configured to form the first lower bridge-arm switch of the first bridge arm, and the plurality of second cell groups are configured to form the second lower bridge-arm switch of the second bridge arm. (0)

20. The integrated power package according to claim 13, wherein the plurality of first cell groups have a plurality of first external pins, the plurality of second cell groups have a plurality of second external pins, a geometric center of at least one of said first and second external pins overlaps with a surface of the chip. (0)

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Application US20190146541

ALTERNATINGLY-SWITCHED PARALLEL CIRCUIT, INTEGRATED POWER MODULE AND INTEGRATED POWER PACKAGE

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