Patent US10445651

Vertical superconducting capacitors for transmon qubits
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US10445651

1. A vertical q-capacitor comprising: (5) (4)

a superconducting material deposited in a trench that is substantially orthogonal to a plane of fabrication, wherein deposited superconducting material forms a first film of the superconducting material on a first surface of the trench, and a second film of the superconducting material on a second surface of the trench, wherein the second surface is substantially parallel to the first surface;

a dielectric between the first film and the second film;

a first coupling between the first film and a first contact in a superconducting quantum logic circuit; and

a second coupling between the second film and a second contact in the superconducting quantum logic circuit, the first coupling and the second coupling causing the first film and the second film to operate as the vertical q-capacitor that maintains integrity of data in the superconducting quantum logic circuit within a threshold level.

2. The vertical q-capacitor of claim 1, further comprising: (0) (1)

3. The vertical q-capacitor of claim 1, further comprising: (2) (6)

a structure formed using a second dielectric material,

wherein the trench comprises a first trench and a second trench, wherein the depth of the trench is a first depth of the first trench, and a second depth of the second trench is substantially parallel to the first depth of the first trench,

wherein the structure is formed between the first trench and the second trench,

wherein the first surface of the trench comprises a surface of the first trench formed by the structure,

wherein the second surface of the trench comprises a surface of the second trench formed by the structure, and

wherein a surface of the structure separates the first surface and the second surface.

4. The vertical q-capacitor of claim 3, wherein the second dielectric material of the structure comprises a material of the substrate. (0)

5. The vertical q-capacitor of claim 3, further comprising: (0) (1)

6. The vertical q-capacitor of claim 1, further comprising: (0) (2)

7. The vertical q-capacitor of claim 1, further comprising: (0) (1)

8. The vertical q-capacitor of claim 1, wherein the superconducting material is Niobium (Nb) and the substrate comprises high-resistivity Silicon (Si). (0)

9. A method comprising: (5) (3)

depositing a superconducting material in a trench that is substantially orthogonal to a plane of fabrication, wherein deposited superconducting material forms a first film of the superconducting material on a first surface of the trench, and a second film of the superconducting material on a second surface of the trench, wherein the second surface is substantially parallel to the first surface;

exposing a dielectric material between the first film and the second film; and

coupling the first film to a first contact in a superconducting quantum logic circuit and the second film to a second contact in the superconducting quantum logic circuit, the coupling causing the first film and the second film to operate as the vertical q-capacitor that maintains integrity of data in the superconducting quantum logic circuit within a threshold level.

10. The method of claim 9, further comprising: (0) (2)

11. The method of claim 9, further comprising: (2) (6)

creating, as a part of forming the trench, a structure of a second dielectric material,

wherein the structure is formed between the first trench and the second trench,

wherein the first surface of the trench comprises a surface of the first trench formed by the structure,

wherein the second surface of the trench comprises a surface of the second trench formed by the structure, and

wherein a surface of the structure separates the first surface and the second surface.

12. The method of claim 11, wherein the second dielectric material of the structure comprises a material of the substrate. (0)

13. The method of claim 11, further comprising: (0) (2)

14. The method of claim 9, further comprising: (0) (2)

15. The method of claim 9, further comprising: (0) (1)

16. The method of claim 9, wherein the superconducting material is Niobium (Nb) and the substrate comprises high-resistivity Silicon (Si). (0)

17. A semiconductor fabrication system comprising a lithography component, the semiconductor fabrication system when operated to fabricate a semiconductor device performing operations comprising: (5) (3)

exposing a dielectric material between the first film and the second film; and

18. The semiconductor fabrication system of claim 17, further comprising: (0) (2)

19. The semiconductor fabrication system of claim 17, further comprising: (2) (6)

creating, as a part of forming the trench, a structure of a second dielectric material,

wherein the structure is formed between the first trench and the second trench,

wherein the first surface of the trench comprises a surface of the first trench formed by the structure,

wherein the second surface of the trench comprises a surface of the second trench formed by the structure, and

wherein a surface of the structure separates the first surface and the second surface.

20. The semiconductor fabrication system of claim 19, wherein the second dielectric material of the structure comprises a material of the substrate. (0)

21. The semiconductor fabrication system of claim 19, further comprising: (0) (2)

22. The semiconductor fabrication system of claim 17, further comprising: (0) (2)

23. The semiconductor fabrication system of claim 17, further comprising: (0) (1)

24. The semiconductor fabrication system of claim 17, wherein the superconducting material is Niobium (Nb) and the substrate comprises high-resistivity Silicon (Si). (0)

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Patent US10445651

Vertical superconducting capacitors for transmon qubits

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