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Patent US10446736
Issued 2019-10-15
Backside Coupling With Superconducting Partial Tsv For Transmon Qubits
A capacitive coupling device (superconducting C-coupler) includes a trench formed through a substrate, from a backside of the substrate, reaching a depth in the substrate, substantially orthogonal to a plane of fabrication on a frontside of the substrate, the depth being less than a thickness of the substrate. A superconducting material is deposited as a continuous conducting via layer in the trench with a space between surfaces of the via layer in the trench remaining accessible from the backside. A superconducting pad is formed on the frontside, the superconducting pad coupling with a quantum logic circuit element fabricated on the frontside. An extension of the via layer is formed on the backside. The extension couples to a quantum readout circuit element fabricated on the backside.
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- 1. A capacitive coupling device (superconducting C-coupler) comprising:
a trench through a substrate, from a backside of the substrate, reaching a depth in the substrate, substantially orthogonal to a plane of fabrication on a frontside of the substrate, the depth being less than a thickness of the substrate; a superconducting material deposited as a via layer in the trench with a space between surfaces of the via layer in the trench remaining accessible from the backside; a superconducting pad on the frontside, the superconducting pad coupling with a quantum logic circuit element fabricated on the frontside; and an extension of the via layer on the backside, wherein the extension couples to a quantum readout circuit element fabricated on the backside.
- 11. A method comprising:
forming, in a capacitive coupling device (superconducting C-coupler), a trench through a substrate, from a backside of the substrate, reaching a depth in the substrate, substantially orthogonal to a plane of fabrication on a frontside of the substrate, the depth being less than a thickness of the substrate; depositing a superconducting material as a via layer in the trench with a space between surfaces of the via layer in the trench remaining accessible from the backside; forming a superconducting pad on the frontside, the superconducting pad coupling with a quantum logic circuit element fabricated on the frontside; and forming an extension of the via layer on the backside, wherein the extension couples to a quantum readout circuit element fabricated on the backside.
