Search All Patents in Quantum Computing
Patent US10411713
Issued 2019-09-10
Superconducting Circuits Based Devices And Methods
Superconducting circuits based devices and methods, including reciprocal quantum logic (RQL) based devices and methods are provided. In one example, a device comprising an output terminal, a first input terminal for receiving a first set of pulses, and a second input terminal for receiving a second set of pulses is provided. The first section may be configured to pass a single pulse received during a single clock cycle at any of the first input terminal or the second input terminal, but to not pass two or more positive pulses received during a single clock cycle at the first input terminal and the second input terminal. The second section, coupled to the first section, may be configured to, in response to the single pulse, generate a negative pulse after a predetermined fraction of a single clock cycle after providing a positive pulse at the output terminal.
Much More than Average Length Specification
View the Patent Matrix® Diagram to Explore the Claim Relationships
USPTO Full Text Publication >
- 1. A device comprising:
an output terminal; a first input terminal for receiving a first set of pulses; a second input terminal for receiving a second set of pulses; a first section configured to pass a single pulse received during a single clock cycle at any of the first input terminal or the second input terminal, but to not pass two or more positive pulses received during a single clock cycle at the first input terminal and the second input terminal, wherein the first section comprises an unpowered stage comprising: (1) a first unpowered Josephson junction coupled between the first input terminal and a second terminal, and (2) a second unpowered Josephson junction coupled between the second input terminal and the second terminal, and wherein the unpowered stage is configured to pass pulses traveling in a first direction, wherein the first direction comprises a direction of travel of any pulses from any of the first input terminal or the second input terminal toward the output terminal and block pulses traveling in a second direction, opposite to the first direction; and a second section, coupled to the first section, wherein the second section is configured to, in response to the single pulse, generate a negative pulse after a predetermined fraction of a single clock cycle after providing a positive pulse at the output terminal.
- 12. A method of operating a device comprising a first input terminal for receiving a first set of pulses, a second input terminal for receiving a second set of pulses, and an output terminal, the method comprising:
passing a single pulse received during a single clock cycle at any of the first input terminal or the second input terminal, but not passing two or more positive pulses received during a single clock cycle at the first input terminal and the second input terminal; passing pulses traveling in a first direction, wherein the first direction comprises a direction of travel of any pulses from any of the first input terminal or the second input terminal toward the output terminal and blocking pulses traveling in a second direction, opposite to the first direction; and in response to the single pulse, generating a negative pulse after a predetermined fraction of a single clock cycle after providing a positive pulse at the output terminal.
- 14. An exclusive OR (XOR) logic gate comprising:
an output terminal; a first input terminal for receiving a first set of pulses; a second input terminal for receiving a second set of pulses; an unpowered stage comprising: (1) a first unpowered Josephson junction coupled between the first input terminal and a second terminal, and (2) a second unpowered Josephson junction coupled between the second input terminal and the second terminal, wherein the unpowered stage is configured to pass pulses traveling in a first direction, wherein the first direction comprises a direction of travel of any pulses from any of the first input terminal or the second input terminal toward the output terminal and block pulses traveling in a second direction, opposite to the first direction; a central junction coupled between the second terminal and a third terminal, wherein the central junction is configured to pass a single pulse, received during a single clock cycle, but block two or more pulses, received during a single clock cycle; and a Josephson transmission line (JTL) network coupled between the third terminal and the output terminal, wherein the JTL network is configured to generate the negative pulse after the predetermined fraction of the single clock cycle after providing the positive pulse at the output terminal.
